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STK10C68
ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to Ground . . . . . . . . . . . . . .-0.5V to 7.0V Voltage on Input Relative to VSS . . . . . . . . . . -0.6V to (VCC + 0.5V) Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC + 0.5V) Temperature under Bias . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA
Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS
SYMBOL ICC b
1
(VCC = 5.0V 10%)
COMMERCIAL MIN MAX 85 75 65 N/A 3 10 27 23 20 N/A 750 1 5 2.2 VSS - .5 2.4 0.4 0 70 -40/-55 VCC + .5 0.8 2.2 VSS - .5 2.4 0.4 85/125 INDUSTRIAL/ MILITARY MIN MAX 90 75 65 55 3 10 28 24 21 20 1500 1 5 VCC + .5 0.8 mA mA mA mA mA mA mA mA mA mA A A A V V V V C tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns tAVAV = 55ns All Inputs Don't Care, VCC = max W (V CC - 0.2V) All Others Cycling, CMOS Levels tAVAV = 25ns, E VIH tAVAV = 35ns, E VIH tAVAV = 45ns, E VIH tAVAV = 55ns, E VIH E (V CC - 0.2V) All Others VIN 0.2V or (VCC - 0.2V) VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G VIH All Inputs All Inputs IOUT = - 4mA IOUT = 8mA UNITS NOTES
PARAMETER
Average VCC Current
ICC c
2 3
Average VCC Current during STORE Average VCC Current at tAVAV = 200ns 5V, 25C, Typical Average VCC Current (Standby, Cycling TTL Input Levels)
ICC b ISB d
1
ISB d
2
VCC Standby Current (Standby, Stable CMOS Input Levels) Input Leakage Current Off-State Output Leakage Current Input Logic "1" Voltage Input Logic "0" Voltage
IILK IOLK VIH VIL VOH VOL TA
Note a: Output Logic "1" Voltage
Output Logic "0" Voltage Operating Temperature
Note b: ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. 1 3 Note c: ICC is the average current required for the duration of the STORE cycle (tSTORE ) . 2 Note d: E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
5.0V
480 Ohms OUTPUT 255 Ohms
CAPACITANCEe
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance
(TA = 25C, f = 1.0MHz)
MAX 8 7 UNITS pF pF CONDITIONS
V = 0 to 3V V = 0 to 3V
30 pF INCLUDING SCOPE AND FIXTURE
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
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SRAM READ CYCLES #1 & #2
SYMBOLS NO. 1 2 3 4 5 6 7 8 9 10 11 #1, #2 tELQV tAVAVf tAVQVg tGLQV tAXQXg tELQX tEHQZh tGLQX tGHQZh tELICCHe tEHICCLd, e Alt. tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS PARAMETER Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold after Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby 0 25 0 10 0 35 5 5 10 0 10 0 45 25 25 10 5 5 10 0 12 0 55 STK10C68-25 MIN MAX 25 35 35 15 5 5 12 0 12 STK10C68-35 MIN MAX 35 45 45 20 5 5 12 MIN
(VCC = 5.0V 10%)
STK10C68-45 MAX 45 55 55 25 STK10C68-55 MIN MAX 55 UNITS ns ns ns ns ns ns ns ns ns ns ns
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. NE must be high during entire cycle. Note g: I/O state assumes E, G < VIL, W > VIH , and NE VIH; device is continuously selected. Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
tAVAV ADDRESS tAXQX DQ (DATA OUT)
5 3 2
tAVQV DATA VALID
SRAM READ CYCLE #2: E Controlledf
tAVAV ADDRESS tELQV E
6 tELQX 1 1 1 2
tEHICCL
7
tEHQZ
G
8 tGLQX
tGLQV
4
tGHQZ
9
DQ (DATA OUT) tELICCH ICC
STANDBY 10 ACTIVE
DATA VALID
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SRAM WRITE CYCLES #1 & #2
NO. 12 13 14 15 16 17 18 19 20 21 SYMBOLS #1 tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX tWLQZh, i tWHQX #2 tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX Alt. tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW PARAMETER Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold after End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold after End of Write Write Enable to Output Disable Output Active after End of Write 5 STK10C68-25 MIN 25 20 20 10 0 20 0 0 10 5 MAX STK10C68-35 MIN 35 25 25 12 0 25 0 0 13 5 MAX MIN 45 30 30 15 0 30 0 0 14 5
(VCC = 5.0V 10%)
STK10C68-45 MAX STK10C68-55 MIN 55 45 45 30 0 45 0 0 15 MAX UNITS ns ns ns ns ns ns ns ns ns ns
Note i: Note j:
If W is low when E goes low, the outputs remain in the high-impedance state. E or W must be VIH during address transitions. NE VIH.
SRAM WRITE CYCLE #1: W Controlledj
tAVAV ADDRESS tELWH E
14 19 12
tWHAX
18 tAVWL
tAVWH tWLWH
15 13
17
W
tDVWH DATA IN tWLQZ DATA OUT
PREVIOUS DATA HIGH IMPEDANCE 20 DATA VALID
16 tWHDX
tWHQX
21
SRAM WRITE CYCLE #2: E Controlledj
tAVAV ADDRESS tAVEL E
18 14 19 12
tELEH
tEHAX
tAVEH W tWLEH
15 16 13
17
tDVEH DATA IN DATA OUT
HIGH IMPEDANCE DATA VALID
tEHDX
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STORE INHIBIT/POWER-UP RECALL
NO. 22 23 24 25 SYMBOLS Standard tRESTORE tSTORE VSWITCH VRESET Power-up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level Low Voltage Reset Level PARAMETER
(VCC = 5.0V + 10%)
STK10C68 MIN MAX 550 10 4.0 4.5 3.6 UNITS NOTES s ms V V k
Note k:
tRESTORE starts from the time VCC rises above VSWITCH.
STORE INHIBIT/POWER-UP RECALL
VCC
5V 24 VSWITCH 25 VRESET
STORE INHIBIT
POWER-UP RECALL 22 tRESTORE DQ (DATA OUT)
POWER-UP RECALL
BROWN OUT STORE INHIBIT NO RECALL (VCC DID NOT GO BELOW VRESET)
BROWN OUT STORE INHIBIT NO RECALL (VCC DID NOT GO BELOW VRESET)
BROWN OUT STORE INHIBIT RECALL WHEN VCC RETURNS ABOVE VSWITCH
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MODE SELECTION
E H L L L L L L W X H L H L L H G X L X L H L H NE X H H L L L X MODE Not Selected Read SRAM Write SRAM Nonvolatile RECALLl Nonvolatile STORE No Operation POWER Standby Active Active Active ICC2 Active
Note l:
An automatic RECALL takes place at power up, starting when VCC exceeds 4.25V and taking tRESTORE.
STORE CYCLES #1 & #2
NO. 26 27 28 29 30 31 32 tNLWL tELWL tWLEL SYMBOLS #1 tWLQXm tWLNHn #2 tELQX tELNH Alt. tSTORE tWC STORE Cycle Time STORE Initiation Cycle Time Output Disable Set-up to NE Fall tGHEL tNLEL Output Disable Set-up to E Fall NE Set-up Chip Enable Set-up Write Enable Set-up PARAMETER
(VCC = 5.0V 10%)
MIN MAX 10 20 0 0 0 0 0 UNITS ms ns ns ns ns ns ns
tGHNL
Note m: Measured with W and NE both returned high, and G returned low. STORE cycles are inhibited below 4.0V. Note n: Once tWC has been satisfied by NE, G, W and E, the STORE cycle is completed automatically. Any of NE, G, W or E may be used to terminate the STORE initiation cycle. Note o: If E is low for any period of time in which W is high while G and NE are low, then a RECALL cycle may be initiated.
STORE CYCLE #1: W Controlledo
NE
G W
28 tGHNL
30 tNLWL
27 tWLNH
E
31 tELWL
HIGH IMPEDANCE
DQ (DATA OUT)
26 tWLQX
STORE CYCLE #2: E Controlledo
NE
30 tNLEL 29 tGHEL
G W E
32 tWLEL 27 tELNH
HIGH IMPEDANCE
DQ (DATA OUT)
26 tELQX
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RECALL CYCLES #1, #2 & #3
NO. 33 34 35 36 37 38 39 40 SYMBOLS #1 tNLQXp tNLNHq #2 tELQXR tELNHR tNLEL #3 tGLQXR tGLNH tNLGL RECALL Cycle Time RECALL Initiation Cycle Time NE Set-up Output Enable Set-up tWHGL tELGL Write Enable Set-up Chip Enable Set-up NE Fall to Outputs Inactive Power-up RECALL Duration 20 0 0 0 0 20 550 PARAMETER
(VCC = 5.0V 10%)
MIN MAX 20 UNITS s ns ns ns ns ns ns s
tGLNL
tWHNL tELNL tNLQZ tRESTORE
tGLEL tWHEL tGLEL
Note p: Measured with W and NE both high, and G and E low. Note q: Once tNLNH has been satisfied by NE, G, W and E, the RECALL cycle is completed automatically. Any of NE, G or E may be used to terminate the RECALL initiation cycle. Note r: If W is low at any point in which both E and NE are low and G is high, then a STORE cycle will be initiated instead of a RECALL.
RECALL CYCLE #1: NE Controlledo
NE G
34 tNLNH 36 tGLNL
W
37 tWHNL 38 tELNL 33 tNLQX
HIGH IMPEDANCE
E
39 tNLQZ
DQ (DATA OUT)
RECALL CYCLE #2: E Controlledo
NE
35 tNLEL 36 tGLEL
G
W E
37 tWHEL
34 tELNHR 33 tELQXR
DQ (DATA OUT)
HIGH IMPEDANCE
RECALL CYCLE #3: G Controlledo, r
NE G
35 tNLGL 34 tGLNH
tWHGL
W E
37
tELGL 33 tGLQXR
38
DQ (DATA OUT)
HIGH IMPEDANCE
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DEVICE OPERATION
The STK10C68 has two modes of operation: SRAM mode and nonvolatile mode, determined by the state of the NE pin. When in SRAM mode, the memory operates as a standard fast static RAM. While in nonvolatile mode, data is transferred in parallel from SRAM to Nonvolatile Elements or from Nonvolatile Elements to SRAM.
NONVOLATILE STORE
A STORE cycle is performed when NE, E and W and low and G is high. While any sequence that achieves this state will initiate a STORE, only W initiation (STORE cycle #1) and E initiation (STORE cycle #2) are practical without risking an unintentional SRAM WRITE that would disturb SRAM data. During a STORE cycle, previous nonvolatile data is erased and the SRAM contents are then programmed into nonvolatile elements. Once a STORE cycle is initiated, further input and output are disabled and the DQ0-7 pins are tri-stated until the cycle is complete. If E and G are low and W and NE are high at the end of the cycle, a READ will be performed and the outputs will go active, signaling the end of the STORE.
NOISE CONSIDERATIONS
Note that the STK10C68 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1F connected between VCC and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems.
SRAM READ
The STK10C68 performs a READ cycle whenever E and G are low and NE and W are high. The address specified on pins A0-12 determines which of the 8,192 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high or W or NE is brought low.
NONVOLATILE RECALL
A RECALL cycle is performed when E, G and NE are low and W is high. Like the STORE cycle, RECALL is initiated when the last of the four clock signals goes to the RECALL state. Once initiated, the RECALL cycle will take tNLQX to complete, during which all inputs are ignored. When the RECALL completes, any READ or WRITE state on the input pins will take effect. Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the nonvolatile cells. The nonvolatile data can be recalled an unlimited number of times. As with the STORE cycle, a transition must occur on any one control pin to cause a RECALL, preventing inadvertent multi-triggering. On power up, once VCC exceeds the VCC sense voltage of 4.25V, a RECALL cycle is automatically initiated. Due to this automatic RECALL, SRAM operation cannot commence until tRESTORE after VCC exceeds approximately 4.25V.
SRAM WRITE
A WRITE cycle is performed whenever E and W are low and NE is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low.
POWER-UP RECALL
During power up, or after any low-power condition (VCC < 3.0V), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of 4.25V, a RECALL cycle will automatically be initiated and will take tRESTORE to complete.
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If the STK10C68 is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected either between W and system VCC or between E and system VCC.
LOW AVERAGE ACTIVE POWER
The STK10C68 draws significantly less current when it is cycled at times longer than 55ns. Figure 2 shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Figure 3 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK10C68 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the VCC level; and 7) I/O loading.
HARDWARE PROTECT
The STK10C68 offers two levels of protection to suppress inadvertent STORE cycles. If the control signals (E, G, W and NE) remain in the STORE condition at the end of a STORE cycle, a second STORE cycle will not be started. The STORE (or RECALL) will be initiated only after a transition on any one of these signals to the required state. In addition to multi-trigger protection, STOREs are inhibited when VCC is below 4.0V, protecting against inadvertent
STOREs.
100
100
Average Active Current (mA)
60
Average Active Current (mA)
80
80
60 TTL CMOS 20
40 TTL 20 CMOS 0 50 100 150 Cycle Time (ns) 200
40
0 50 100 150 Cycle Time (ns) 200
Figure 2: ICC (max) Reads
Figure 3: ICC (max) Writes
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STK10C68 ORDERING INFORMATION STK10C68 - 5 P F 45 I Temperature Range
Blank = Commercial (0 to 70C) I = Industrial (-40 to 85C) M = Military (-55 to 125C)
Access Time
25 = 25ns 35 = 35ns 45 = 45ns 55 = 55ns (Military only)
Lead Finish (Plastic only)
Blank = 85%Sn/15%Pb F = 100% Sn (Matte Tin)
Package
P = Plastic 28-pin 300 mil DIP S = Plastic 28-pin 350 mil SOIC C = Ceramic 28-pin 300 mil DIP (gold lead finish) K = Ceramic 28-pin 300 mil DIP (solder dip finish) L = Ceramic 28 pin LCC
Retention / Endurance
Blank = Comm/Ind (100 years/106cycles) 5 = Military (10 years/105cycles)
5962-93056 04 MX X Lead Finish
A = Solder DIP lead finish C = Gold lead DIP finish X = Lead finish "A" or "C" is acceptable
Package
MX = Ceramic 28 pin 300-mil DIP MY = Ceramic 28 pin LCC
Access Time
04 = 55ns 05 = 45ns 06 = 35ns
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Document Revision History
Revision 0.0 0.1
Date December 2002 September 2003
Summary Combined commercial, industrial and military data sheets. Removed 20 nsec device. Added lead-free lead finish
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